1. Field of the Invention
This invention relates to the field of data processing systems. More particularly, this invention relates to the encoding of data access program instructions for use in data processing systems.
2. Description of the Prior Art
It is known to provide data processing systems with data access instructions. An example of such a class of program instructions is the LDR/LDRB/STR/STRB class of instructions of the ARM instruction set (see for example the ARM Architecture Reference Manual). These are a group of instructions that are orthogonally encoded with respect to each other, in the sense that they specify different main operations, but each main operation can use the same addressing modes or other sub-operations as all the others. The ARM instruction set is a 32-bit instruction set and the LDR/LDRB/STR/STRB class of instructions contains 20 bits that affect the addressing mode calculation:
4 bits (bits[19:16]) to specify the base register;
13 bits (bit[25] and bits[11:0]) to specify either a 12-bit immediate offset (a first form of the instruction) or an index register and a shift (or rotate) to be applied to it (a second form of the instruction); and
3 bits (P=bit[24], U=bit[23], W=bit[21]) to specify the manipulation to be performed on the base register value and the offset. Examples of the addressing modes that may be specified are offset addressing, pre-indexed addressing, post-indexed addressing and unprivileged post-indexed addressing. Such data access instructions provide considerable flexibility in the way that the data access operation may be specified. This helps to reduce the number of instructions required to transfer the desired data to or from memory thereby increasing speed and improving code density.
A common problem within data processing systems is that the encoding bit space available is a finite resource and competing demands are made upon this encoding bit space for different types of instructions which may be useful in different circumstances. It is often the case that the number of potentially useful instructions that might be provided exceeds the encoding bit space available within the processor architecture. Accordingly, measures which can improve the efficiency of use of the encoding bit space are strongly advantageous.